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Programmable Logic: What’s it to Ya?
by Michael Barr from Embedded Systems Programming, June 1999
6 pages

This document gives a basic overview of common programmable logic hardware: FPGA’s, CPLD’s and PLD. (Hold the mouse over links and acronyms to see their full definition or click to follow to their wikipedia entries).

PLD
In the beginning there was PLD, and it was good. PLD let you take simple Logic Gate (AND/OR/NOT, etc.) TTL components and combine them into one chip. It is also known as GAL, PLA and PAL.

CPLD
PLD * n. CPLD’s combine various common PLD configurations into one component. A switch matrix is used to control IO between, to and from each. A CPLD differers from an FPGA in that not all logical components are equal in a CPLD. Because of this one must choose their CPLD wisely, according to their application. The benefit it provides however is that an application could run faster on an optimized CPLD than it would on the ever flexible FPGA.

FPGA
Unlike a CPLD the logical unit of an FPGA is much smaller containing only a few small logic gates. The structure of the hardware itself separates tasks into IO blocks around the perimeter of the chip with the Logic blocks residing in a matrix inside. FPGA’s are measured by the number of logical gates (gate count), I/O pins and use of ROM or RAM.

VHDL or Verilog are used to describe a highlevel architecture for use in an FPGA. These languages are general enough however to be applied to CPLD’s. They are used in general ASIC design as well. Typically one then uses simulation tools (such as those provided by Cadence) to simulate the high level logic. After simulation one would move to compilation.

Synthesis, the next step, is the process of taking a high level design and producing a Netlist. The netlist is still device independent. It is stored in a format called EDIF.

Place & Route, the step after producing a netlist, involves “mapping the logical structures described in the netlist onto actual macrocells, interconnections and input and output pins.” The result is a bitstream downloaded to the actual device. The bitstream format is device dependent.

Download to the device of the bitstream format is a process which depends on the features of the device. For FPGA’s that use EPROM to store their definitions one might either need to place the FPGA in a programmer or use JTAG, if the FPGA has separate logic defined for supporting this onboard. For FPGA’s that use RAM instead of ROM they must support some dynamic programming. An advantage of RAM based FPGA’s is that definitions can be changed on the fly (swap out DES logic for AES as you please). However they do consume more power and the original definition/bitstream must be reloaded on every power refresh.